Many modern processors control various input/output (“I/O”) devices using a memory-mapped I/O scheme, which enables a processor to communicate to an I/O device by reading and writing to one or more memory addresses reserved for that particular I/O device. A drawback of this approach, however, is that the memory addresses reserved for each I/O device reduces system memory available to the processor, such as when the reserved addresses coincide with physical addresses. Collectively, those reserved addresses constitute a “memory hole,” which is a term commonly used to describe the linear address space of the memory that is unusable (or inaccessible) to a processor as system memory. As the number of I/O devices increases, the range of linear addresses reserved to service those I/O devices increases correspondingly. Consequently, the amount of memory useable as system memory decreases. To illustrate the effects of memory holes on system memory, consider a 36-bit processor having access greater than 4 GB of memory (i.e., an amount of memory including 236 addresses) and being a part of a computing system having two graphics processing units (“GPUs”) as I/O devices. Usually, each of these GPUs can require 1024 megabytes (MB) of address space (i.e., an amount of memory including 230 addresses) in system memory to maintain frame buffers, which would then require reserving a total amount of 2 gigabytes (“GB”) of address space to cover the two GPUs. Moreover, additional system memory must be dedicated for boot code and for other I/O devices, such as audio and visual devices. Consequently, the processor of this example would have less than one-half of its system memory available to perform its computational tasks. So if reserved memory were to expand without bound, processors would be left without much system memory with which to operate.
There are several memory addressing techniques known for redirecting accesses from one range of addresses of memory to another range of addresses. Some of these techniques are used for reducing the effects of memory holes, while others are directed toward other memory management functions.
FIG. 1A illustrates one memory addressing technique used for ameliorating the effects of memory holes. In this approach, system memory 100 is increased by adding extended memory 102 to the normal amount of memory available (“useable memory”) 108 that is useable by a processor (not shown), which typically is about 680 kilobytes (“KB”). By adding extended memory 102, system memory 100 recovers the 340 KB of system memory usually lost to memory hole 104. In this memory addressing technique, an arithmetic operator 106 adds an amount, “delta,” to a linear address (“LA”) 101 to form adjusted address 103 (i.e., LA+delta), but only if address 101 is above 640 KB. The amount delta is a single quantity of addresses representing a displacement in linear address space. Arithmetic operator 106 therefore uses addition to redirect address 101 from a reserved address space in memory hole 104 to the supplemental address space in extended memory 102, thereby recovering memory that otherwise would not be available to the processor. While functional, adding an amount “delta” to an address is relatively cumbersome in execution and requires more hardware to implement adders than otherwise is necessary to reduce the effects of memory holes.
FIG. 1B shows another conventional memory addressing technique for managing memory. In this technique, system memory 150 contains three disparately sized dual in-line memory modules (“DIMMs”), such as DIMM (“1”) 154, DIMM (“2”) 152 and DIMM (“3”) 156, that are collectively divided into ranges of linear addresses 162. Each range 162 corresponds to a range of physical addresses and has a range base 166 describing a base address for that range. For example, Range 1, which extends from linear address (“LA”) 2 GB to LA 3 GB, has a range base (“1”) 166b of 2 GB. As such, linear addresses from 0 GB to 2 GB map into physical addresses 0 GB to 1 GB−1 of DIMM (“1”) 154, as translated from range base (“0”) 166c, and linear addresses 2 GB to 3 GB map into physical addresses 1 GB to 2 GB−1 of DIMM (“1”) 154, as translated from range base (“1”) 166b. A DIMM base address (“DIMM Base”) 170 is selected to relate a linear address, such as “LA 2 GB+1,” to the physical addresses of system memory 150. Notably, linear addresses of a memory hole 168 also correspond to physical addresses in system memory, and specifically, to a group 164 of physical addresses that includes data for memory-mapped I/O devices. As such, a processor cannot use group 164 of physical addresses to process computations. While functional in addressing some system memories, this conventional memory technique does not ameliorate the effects of memory holes and is not readily adaptable to do so.
In view of the foregoing, it would be desirable to provide a system, an apparatus and a method for minimizing the drawbacks of the above-mentioned memory addressing techniques in the reclamation of memory in any number of arbitrarily-sized memory devices that otherwise would be lost to a memory hole.